The present invention relates to functions that can be performed by field programmable gate arrays (FPGAs) and uses made of FPGAs.
Field programmable gate arrays (FPGAs) are integrated circuits programmable by a user to perform complex functions. They include logic blocks and routing lines. The logic blocks typically include lookup tables that perform any function of the input signals. For example, a four-input lookup table can perform any of over 65,000 functions of the four input signals. The routing lines can be connected to carry signals between the logic blocks. Programming of the FPGA is performed by loading a bitstream of 0""s and 1""s into an array of memory cells that connect or don""t connect routing lines to each other and to the logic blocks, and that store the values of the lookup tables. The memory cells also program multiplexers that route internal signals within the logic blocks. The first FPGA is described by Freeman in U.S. Reissue Patent Re 34,363. A more recent FPGA is described by Young et al. in U.S. Pat. No. 5,914,616. The information in these patents is incorporated herein by reference.
One feature of more recent FPGAs is logic blocks usable as dual port RAMS. Freidin et al. in U.S. Pat. No. 5,566,123 describe a synchronous dual port RAM. Also available in more recent FPGAs are blocks of RAM memory accessible to the logic blocks. Young in U.S. Pat. No. 5,933,023 describes one such structure. These patents are also incorporated herein by reference.
The true dual-port structure of the block RAMs includes input and output data buses plus address and control signals for each port. Data can be independently read from and written to each port. Both read and write accesses are synchronized to the appropriate port clock, with a positive or negative selectable edge. The only operational limitation is not to write data to a given address from one port while it is being read from the other port.
The block memories in the Virtex(trademark)-II FPGA architecture available from Xilinx, Inc., assignee of the present invention, are capable of supporting data bus widths of up to 36-bits. To allow for parity, the basic array size of the block memory is 18 Kbits. Each port may be independently configured for a specific data bus width. For example, Port A can be configured as a 512xc3x9736 memory, and port B configured differently as a 2048xc3x979 memory. Using these features, clock domains are safely crossed at the same time as the data width is converted. As an example, the output buffer on a communication system could use 36-bit wide data written at 50 MHz, and read as 9-bit wide data at 155 MHz. All the various combinations of memory structure are shown in Table 1.
It is known to use FPGAs to form first-in-first-out (FIFO) memories. Alfke in U.S. Pat. Ser. No. 5,898,893 describes such a FIFO. This patent is incorporated herein by reference. A FIFO stores data in sequential memory locations and uses a read counter for determining which memory location to read next and a write counter for determining which memory location to write to next. The read and write counters are controlled by independent clock signals provided by the devices that are writing to and reading from the FIFO.
According to the invention, a self-addressing FIFO uses these block memories to store both data and address information in a single memory location. Thus, no external counters are required for incrementing the address. The self-addressing FIFO counters are implemented as a ROM based sequencer inside the same memory being used for data storage. Only flag and status information logic are used. An advantage of the invention is in using only one clock load. Thus, clock skew does not occur. In addition, the status mechanism is very simple. These FIFOs are desirable for data throttling in continuous data systems more than for use when full or empty detection is frequently required in frame based data systems. The self-addressing FIFO is a small and novel mechanism for transferring data between clock domains while avoiding the necessity of using a clock tree. The only constraints are that data must be valid at the clock edges and the clock period still needs to be controlled. Since clock skew is not an issue, general purpose routing may be used for the input and output clocks, depending on the system architecture.